In the past, wafer topography inspection was accomplished with bright light and the naked eye, by field-at-a-time microscope inspection, or by laboratory methods such as X-ray topography and Transmission Electron Microscopy (TEM). A full-field, submicron visual inspection system is now available to address inspection requirements between those that can be satisfied by naked-eye visual inspection and those that require complex laboratory equipment.

Real Time Visual Inspection

This new technology is implemented in the no-contact, surface-monitoring tool, shown in Figure l, that transforms hard-to-find damage, slip lines, texture, dimples, polish marks, etc., on mirror-like surfaces into visual images. Shallow damage, hidden in the wafer's top layer and often invisible to human eye inspection (even when aided by bright light or a microscope), is made visible on the system's video monitor.

Unlike analytical lab equipment, that may destroy the wafer surface during its inspection, this technique is non-destructive to wafer surfaces. The equipment permits realtime surface inspection of submicron (peak to-valley) defects with sensitivity to the level of undulation of less than l0 nm over a distance of approximately 0.5 mm.

The visual inspection technology is based on the "Makyoh" principle. The key element of this optical observat on method is a high intensity light source that impinges on, and is then viewed from, a mirror surface.

"Makyoh mirrors" have been kept for centuries in ancient shrines in the Far East. These devices are simply flat mirrors, usually made mostly of brass, that exhibit no features when being viewed directly, but that reflect images on a wall when the sun or the moon, or some other bright light, is reflected.

The inspection system employs a collimated light source to illuminate the surface to be examined. The light reflected by this surface is then collimated and projected onto a light receiving screen, whereupon the system acts as a surface analyzer that transforms surface irregularities into visual images on a TV monitor.

The intense light source impinges onto polished wafer surfaces at a perpendicular angle. The light reflected from the wafer surface is then projected onto a modified detector assembly. Concave and convex distortions are represented by variations in contrast where convex distortions appear dark and concave distortions appear abnormally bright.

System sensitivity is increased by means of a Charge-Coupled-Device (CCD) camera that focuses and analyzes the light reflected from the wafer surface. A compact monochromatic LED is used as a point-like light source and the CCD, which is sensitive to visible light, is used as the screen. Specific shading patterns, lines, stripes, or dots on the video monitor indicate corresponding surface irregularities of the substrate or thin film, such as an epitaxial layer.

The bright and dark intensity variations displayed on the monitor are related directly to the radius of curvature, R, of the corresponding irregularities. On a nearly perfect mirror surface, irregularities with radii of curvature ranging from approximately 1 M to 100 M are detected. The surface irregularities shown in Figure 2 illustrate very shallow concavities of approximately 0.38 µm (380nm) depth over a span of 10 mm and 0.50 µm (500nm) depth over a 1mm span, corresponding to radii of curvature, R, of about 15 M and 2 M, respectively. (These depths were measured by a surface profilometer.) A variety of surface irregularities, as seen on the system's monitor, are presented in Figure 3.

Surface-Anomaly Effect on Yield

Saw marks from slicing of wafers may be harmful because latent crystal defects may be hidden beneath them. During subsequent heat treatment, latent stresses surrounding saw marks can provide potential sites for the formation of stacking faults and dislocations.

Polishing marks may be produced by such things as wax contamination, surface irregularities, fibrous materials, and the texture of polishing cloths. Although they create a slight waviness on the wafer surface, polishing marks do not produce any residual stress, nor do they indicate any probable crystal defects. Consequently, they are not as harmful as saw marks. In the case of dimples, which are localized depressions in the wafer surface, caused by impurities beneath the wafer during polishing, site flatness will be affected, which could lead to exposure defects in lithography.

Because rough grinding may leave large defects that may not be eliminated during subsequent polishing process steps, lapping marks may be harmful. It is difficult to differentiate between polishing and lapping marks. To ascertain whether any symptoms of process variations or instabilities are present, the changes in image patterns must be monitored for a period of time. Typical lapping-mark patterns with widths as great as 0.4 mm (400 µm) can be observed.

Typically, inspection of wafers for thermal slip is accomplished by examination under an optical microscope, using a rotating wafer stage. Although certainly a valid method, such inspection is a monotonous, optically strenuous task that usually fails to detect any slip. This may lull inspectors into a false sense of security, resulting in insufficient inspection that can ultimately lead to failure to detect a minor slip problem for a period of time. Moreover, slip occurring near the center of the wafer surface may go unnoticed during typical multi-point wafer inspections.

To avoid these problems, a full-field, submicron visual inspection system has been applied to wafer inspection for thermal slip. In addition to an order-of-magnitude reduction in inspection time, the inspection is more thorough, and a full-wafer view of the slip pattern makes it easier to correlate the location of the slip with a particular process or equipment problem.

Figure 4 shows thermal slip on a (111) wafer, caused by "boat pinch", and identified by the slip lines protruding from the points of contact. Figure 5 shows center slip, caused by excessive pull rate of wafers from a high-temperature furnace operation. In this case, the close spacing of wafers in the furnace boat caused a much faster convective cooling rate around the periphery of the wafers relative to that of their centers.

Contraction stresses on a wafer are relieved by crystalline slip generation at its center. (Slip in the center of a wafer's surface is much more costly in terms of chip yield than edge slip, which may not extend into the patterned area of the wafer.) The slip shown in Figure 6 resulted from uneven heating across the wafer during temperature ramp in an epitaxial deposition process. The problem was corrected by reducing the ramp rate.

The wafer inspection tool also provides a good means for comparison of slip in wafers processed on equipment from various manufacturers. Figure 7 shows wafers processed in epi reactors from four different suppliers. Comparison of these images provides a qualitative slip evaluation method that can be made quantitative by superimposing an equivalent-area grid upon each wafer and counting the elements intersected by slip lines.

Although not its intended use, the system can even reveal slip on patterned wafers, as illustrated in Figure 8, by adjusting its sensitivity The "Makyoh" technique is also very useful for the identification of aberrations on the surface of incoming wafers. As illustrated in Figure 9, such aberrations include saw marks, dimples, polishing/lapping irregularities, backsurface damage anomalies, and microscratches.

Summary

Characterization of wafer surface imperfections is an important step in identifying and eliminating the cause of such defects. The full-wafer inspection system described provides real-time microtopography images of wafer surfaces to assist in the rapid identification and resolution of process, equipment, or material problems. The system provides a particularly advantageous approach to current methods of crystal slip identification and characterization.

References

C. Yarling and A. Keenan, "Defect Analysis of Rapid Thermal Processing Round Robin Results", MRS Meeting, San Diego, California (1989).
SEMI M17-90, Specification for a Universal Wafer Grid.
S. Hahn and K. Kugimiya, "Characterization of Mirror Polished Silicon Wafers Using 'Makyoh', the Magic-Mirror Method" ECS Silicon Sym posium Meeting, Montreal, Canada (May 1990).