E+H Article
Improvements in Yield by Eliminating Backgrind Defects and Providing Stress Relief with Wet Chemical Etching
Mark Hendrix; ST Microelectronics Carrollton, Texas USA
Scott Drews; SEZ America Phoenix, Arizona USA
As the demand for electronic devices such as memory cards, smart cards, portable communication devices, and portable computers become smaller and have higher performance standards; integrated circuit (IC) package requirements must be reduced in both thickness and in footprint making interconnect pitches and feature sizes smaller in every aspect. These demands require chip and packaging designers to develop high-speed, ultra-thin chips that utilize less individual area and overall package height to access multiple layers of dense interconnects. The chips that are required to fit into these more intelligent devices have to be remarkably thin, which justifies that silicon thinning and stress relief applications are becoming more significant in the backend and assembly areas of semiconductor component manufacturing.

Providing thinner substrates has been important for discrete components and is becoming increasingly so for all technologies as die packages and electrical requirements become more stringent. Packaging is constantly evolving with growth and significant technological changes underway. Further advancements in packaging technology require chips to be smaller in diameter and thinner in depth to meet size constraints, area constraints, and higher thermal reliability. Backgrinding provides a high wafer throughput and continues to be a dominant process in wafer thinning. Removal of the surface damage, microcracks, crystal defects and dislocations, and wafer stress and warpage are a concern with yield loss during handling, de-taping, dicing, and package assembly.

In some applications where wafers are to be thinned to below 180 µm from ~600-700 µm, like smart cards, results from grinding leave high wafer warpage and decrease wafer and die strength. These defects along with surface damage and microcracks can affect device parameters such as contact resistance, voltage, thermal resistance, leakage and lifetime. The amount of damage produced into the silicon during the grinding process depends on several operating parameters such as grit size, table speed, wheel and spindle conditions, and coolant flow. Components of the backgrinding system degrade over periods of processing time, which signifies that a post grind process must be optimized to accommodate the worst processing conditions. The backgrinding process is also limited by the minimum wafer thickness specifications that the system can achieve. Most state of the art grinding systems can thin wafers to 150 µm with significant optimization, but the amount of damage induced into the silicon from this process develops into a larger portion of the remaining bulk silicon.

Non-uniformities within the silicon caused from backgrinding can also cause points to be resolved during the dicing process. Edge chips can occur leaving weak points in the die, which may not endure the stresses generated during the assembly process. Another essential parameter when analyzing a robust thinning process and stress relief process is die strength. Larger die are being assembled into smaller packages, introducing more stress on the die. As there are more technological advancements in stacked chip packaging, backside wafer surface conditioning and stress relief applications become even more essential.
Figure 1. Backside defects on a ground wafer by two wheel infeed grinder.
The backgrind process adds significant stress and warpage to thin silicon wafers that are already stressed from device layers on the front surface. The top layer of the silicon after backgrind, which is about 5-10 µm thick, is the area with microcracks, which is entirely destroyed silicon. The second underlying layer of the silicon contains crystal dislocations causing degradation of some electrical properties. These effects of backgrinding create increasingly significant risks of yield loss during de-taping, handling, dicing and package assembly processing. Many discrete components require further processing after wafers have gone through a backgrind process. Post backgrind processing may include ion implantation, heat treatments, and backside metal deposition. Thus, it is necessary and important to provide maximized wafer strength and overall wafer uniformity for manufacturing devices with high yield through post backgrind processes, wafer dicing, and packaging.
Eliminating Backgrind Silicon Defects
There have been many series of in-depth studies concerning the elimination of backgrind silicon defects and warpage left behind after a silicon backgrinding thinning process. There are several technology methods for use on the market in post grinding wafer preparation, for example, CMP type, plasma and wet solutions. CMP type and plasma solutions still induce some mechanical damage to the substrate surface. Wet solutions do not produce mechanical damage and are capable of generating a wide range of backside surface properties ranging from highly polished surfaces to semi-rough to rough surfaces for high power devices. The technology of wet etching backgrind defects eliminates these imperfections, producing stronger wafers and stronger die. Wet chemical processing of backside silicon thinning and stress relief processes can provide the means to accomplish the wafer thinning, stress relief, and backside surface preparation needs for the emerging technologies. Thinning below 150 µm requires a non-contact transfer method to avoid wafer edge chipping, cracking, and wafer breakage. Wet chemical Spin-Processing equipment, offering a Bernoulli handling system, can handle extremely warped wafers thinner than 100 µm. The same wet processing system can handle full thickness wafers with no need for additional hardware modifications. The transition to 300 mm wafer size introduces another challenge for thinning and handling of such ultra thin substrates.

Using wet chemical process technology for wafer thinning, from 10-100 µm silicon removal, and strength enhancement also allows the user to control the backside wafer surface finish. A smooth or rough backside wafer surface can be achieved with aqueous chemical etchants. Because the roughened backside wafer surface is created with chemicals, it does not introduce propagating crystalline defects, but rather leaves the wafer in an optimum state for back metal adhesion and the reduction of contact resistance in high power devices. Similar results on highly doped boron and arsenic wafers are easily obtained. Although backside silicon etching provides a relatively stress free method of thinning wafers, it has not replaced backgrinding. A faster silicon removal rate can still be achieved through backgrinding. These two processes are typically used in concert. Process engineers determine an optimal combination by balancing the high throughput of backgrinding with the stress and damage removal advantages of etching. Wet processing technology and its accompanying chemical etchants optimize wafer and die strength providing the maximum intrinsic strength to process wafers to their desired thickness.
Figure 2. Ground wafer backside and an additional 100 µm silicon removal with polished finish by Spin-Processing. Figure 3. Ground wafer backside and an additional 100 µm silicon removal with with rough finish by Spin-Processing.
Improvements
Shipped wafer breakage is a common result of backgrinding without adequate wafer and die strength enhancement. ST Microelectronics’ Carrollton fab initially reported itself as the worst device manufacturer within the company in shipped wafer breakage overall. After implementing wet chemical Spin-Processing technology in its 150 mm processing line, the fab incorporated it as their process of record worldwide. Prior to implementing wet chemical processing, the fab reported a loss in yield by offshore assembly sites averaging as high as approximately 14 out of every 24,000 wafers processed. After instituting wet chemical etching to their wafer processing techniques, an improvement in packaging yield to 1 out of every 50,000 wafers processed was reported.

Currently, the fab uses backgrinding technology to thin the back surface of their 150 mm silicon wafers. For one such device, they backgrind to 260 µm using grinders with 320 grit coarse wheels and complete their grinding process with a 1700 grit fine wheel. They then condition the wafer surface using chemical wet etching on the ground wafers. Bulk silicon removal chemistry is used to remove the surface defects from the backgrind wafer surface, such as microcracks, crystal dislocations, and overall wafer stress and warp. A polish surface finish chemistry then follows the bulk silicon removal and stress relief chemistry to provide a high reflective mirror like backside surface.

In-depth studies evaluating the advantages of eliminating backgrind damage on 150 mm wafers processed at this facility showed a significant yield benefit was obtained by using wet chemical process technology in the post backgrind process. Wet chemical etching was incorporated into the post backgrind wafer process in November of 1998. Since then, there has been a 96.5 percent reduction in wafer breakage and scrap of backgrind material with a system uptime of 99.4 percent. Process engineers confirmed that including wet chemical etching after the backgrind process resulted in a decrease in wafer warpage by as much as 85%. Comparison of strength results from whole wafers and die, strength tested with and without wet chemical etching and stress relief, showed wafer strength to be 25 times stronger after wet etching than without on whole wafers, and as high as 200 percent with die alone.i

The measurement tool used was a compact desktop instrument for geometry measurement of silicon wafers with a large thickness range. It contains optional software for stress evaluation and data export. The gauge is based on two heavy steel plates mounted opposite of each other. Each plate contains a set of contactless capacitive sensors with a resolution of 0.1 µm, which are arranged in a star shaped pattern. The wafer is inserted into the air gap between the two plates, it is then positioned on three resting pins for the measurement. The sensors measure the distance to the wafer surface within 5 seconds, and the results are then sent to the connected PC through a serial interface. There is no mechanical movement during the measurement. The supplied PC software computes the distance values into wafer characteristics. Thickness: center-, average-, minimum-, maximum-, total thickness variation (TTV), and local thickness. Flatness: local focal point deviation (FPD), maximum negative FPD, maximum positive FPD, and Total indicator reading (TIR). Warp: local warp, total warp, bow and shape. In conjunction with this measurement tool, a force gauge for analysis from 0 to 50 pounds was used to measure precise strength

values on whole wafers and die. A custom steel base, with a 50 mm radius centered hole and a retaining rim, was made to hold the wafer in place during strength analysis. The whole wafer is then placed device side up within the base. The force gauge then is manually driven toward the wafer center with a ½" steel ball tip as its contact zone. The gauge rod pushes against the device side of the wafer providing digital strength resistance in pounds until the wafer breaks revealing overall wafer strength results. Whole wafer technique was used to eliminate variables injected by die/saw operations thus achieving repeatable true gains in strength.
Analyzing the Strength Results
Figure 4. Whole wafer strength determined with wet chemical Spin Processing time.
The results reveal that a noticeable increase in whole wafer strength does not appear until after five seconds of etch time. At 0 seconds of etch time on a wafer ground to 260 µm, the average strength is 1.8 pounds. After 3 seconds of wet chemical etching and 5 µm silicon removal, the wafer strength increases to an average of 3.15 pounds. At 4 seconds of wet etching, approximately 6.5 µm silicon removal, the wafer strength average almost quadruples the 3 second etch time at 11.2 pounds. At that point, maximized whole wafer strength is achieved after 5 seconds of etch time with a silicon removal amount of 7.3 µm. Average wafer strength at 5 seconds is 45.6 pounds. Maximized whole wafer strength was maintained from 6 seconds of wet chemical etching on a wafer ground to 260 µm, to 15 seconds of process time with an average strength of 48 pounds. Results demonstrate that after 6 seconds of bulk silicon chemical etchant, followed by 4 seconds of polish etchant, with approximately 8 µm of silicon removed using the Spin-Processing technique, average whole wafer strength increased by 25 times presenting increases in yield through post grind processing and packaging.
Analyzing the Warp Results
Significant decreased amounts in 150 mm whole wafer warp were also revealed after incorporating wet chemical processing technology into the process line. These results are shown in Figure 5.
Figure 5. Whole wafer warp determined with wet chemical Spin Processing time.
Results show that the average warpage of a wafer ground to 260 µm was calculated at 269 µm prior to wet chemical etching. After exposing the wafer from a period of 3 to 6 seconds, an average wafer warpage of 27 µm was achieved. This was a decrease in overall wafer warpage of 242 µm, almost ten times less warp and a decrease of 90 percent. As presented in Figure 5, after an etch time of 7 seconds, the decrease in overall wafer warpage lessened by 29 percent. This was caused by the increase in removal of the silicon. As the wafer becomes thinner, the wafer becomes susceptible to warpage. The results after 7 seconds of wet chemical processing were still outstanding. A decrease in warp of 66 percent was achieved. Warpage in general is improved with wet chemical etching, but its extent is entirely dependent upon fab and device processes before backgrind.

The total thickness variations within each wafer and from wafer to wafer, were minimal. Non-uniformities after etch were demonstrated to be values from +/- 3 µm, and less within wafers depending upon the post backgrind uniformity of the wafer’s surface. From wafer to wafer, results show less than 1 µm. As for the cosmetics of the backside of the wafer after backgrind, a process of approximately 11 seconds of bulk silicon etch and 4 seconds of polish etch was needed to remove backgrind damage and marks with a highly polished backside surface.
Conclusion
This study has proven that with flexible wet chemical processing technology, all backend and packaging needs can be met. The technology of wet chemical etching allows fabs to offer stronger, more reliable products to customers. This technology of wafer thinning, warp and stress relief is well tested, implemented and has been refined for over a decade. As new challenges will constantly affect technology advances, process and electrical yields affected by grind defects can be resolved. An optimized stress relief process provides the following benefits:

• Stronger wafers for post grind processing through wafer saw.

• Defect free backsides to prevent intrinsic damage that can cause leakage and problems with minority carrier lifetime and refresh times.

• Stronger die for assembly and reliability concerns, including smaller packages and improved thermal performance.

• Minimized warp and stress to ease handling and packaging concerns.

• Optimal backside surface preparation for improved adhesion characteristics.

Larger diameter wafers will also bring a need for grinding and stress relief process. As the industry’s standard wafer diameter increases to 300 mm and beyond the wafer thickness at which grind damage and lower wafer strength is noticeable will increase and create problems with existing package sizes. These issues will intensify the need for an optimized and controllable backside damage removal and stress relief process.
Acknowledgement
SEZ America

SEZ AG

ST Microelectronics Carrollton, TX USA

Hologenix

Shimpo

Ashland Specialty Chemical Company
References
i The studies of the wafer values were done at ST Microelectronics Carrollton using a Hologenix MX 203 Wafer Profiler to accurately determine ST Carrollton’s strength comparison results.

ii Result values provided by Mark Hendrix of ST Microelectronics Carrollton, Texas USA.
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