PBS 1000
Examples of PBS™ Measurements

The maps on this page and the following pages show PBS™ measurements on various silicon wafers with differing types of defects, or none at all. In some cases the V-MAP (scatter versus angle of the plane of incidence) is included with the area maps if it shows a distinctive feature, otherwise it is not included.

The maps below show a V-MAP (left image) and an area map (center image) for a very high quality defect free, 200mm wafer.

Wafer TEST070 (right image) is an example of a wafer with significant staining. This type of feature is the result of the wafer not sitting flat against the polishing pad, a situation usually caused by debris under the wafer.
Wafer TEST206 has a map with a circular high scatter area in the center. This was caused by the method used to position the wafer in the wax before polishing. As in the case of TEST070, this wafer did not sit flat against the pad during the polishing process.
Wafer TESTG032 is another example of the wafer not sitting flat against the pad. In this case, the center was slightly concave.

Wafer TEST80 is an example of an Epi-wafer that is poor in quality. The red spots at the top of the wafer map (right image) are particles that can be ignored. The main problem is the high scatter level and the circular red area in the center of the map. Typical Epiwafers have a higher scatter level than polished wafers, but are completely uniform. The V-MAP (left image) for this wafer is typical of an Epi-wafer V-MAP showing only one direction, either O or 90 degrees.

The process of making an Epi-wafer can cause serious problems if there is subsurface damage in the substrate. Wafer TESTG23 shows the result of exposure to hydrogen at high temperature. The V-MAP shows a single strong direction at about 40 degrees.
The area map shows obvious polishing damage near the center of the wafer.
The high-resolution area map was made close to the center of the wafer and shows the damage more clearly. The isolated red spots on this map are very small surface pits, which were measured as being 20 to 40nm in diameter. These pits are exposed subsurface damage and generally follow the linear features on the map.
It is also possible to map the backside of certain wafers depending on the level of roughness. Wafers that appear shiny and scatter only a small amount of light can be mapped, including wafers with an oxide layer. The maps of wafer BACK225 show scuff marks (long squiggly lines) which are caused by handling. In addition, other kinds of features are shown which can be isolated with the Surface and Subsurface EPBS™ maps shown below.
The Surface EPBS™ map shows small red spots which are particles and other surface defects.
The Subsurface EPBS™ map isolates growth defects, which can be seen as the center rings and the large outer ring. These defects will change depending on the position of the wafer in the boule.
A PBS® system based on a UV laser is also available. This system uses a 325nm laser and is useful for measuring subsurface defects on SiC and SOI wafers and for surface measurements on silicon wafers. The map for silicon wafer TEST21MR clearly shows three types of features:
  1. point defects (particles, pits, etc.)
  2. scratches, and
  3. possible cleaning stains

The word stain is used here to describe the appearance of the features on the map, but in actuality, these are areas with differing surface roughness characteristics. This variation in roughness is extremely subtle since none of these features, except some of the point defects, show up on the standard PBS® map for this wafer.

The wafer map for TEST21MR shows a large subsurface defect in a 3" diameter GaAs wafer. The defect, in the "T" shaped red area, could not be detected as a surface feature in the Nomarski at 200X or with other standard visual inspection techniques. Delineation etching revealed a high concentration of deep damage traces in the red area of the map. Also, other wafers from the same lot did not show the same damage characteristic. In many cases this type of defect can be caused by debris on the back side of the wafer that does not allow the wafer to sit flat against the pad during polishing.

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